1. Field of the Invention
The present invention relates generally to a field effect transistor formed using a wide-gap semiconductor and to a method of manufacturing the same.
2. Related Background Art
Conventionally, various field effect transistors (insulated-gate semiconductor devices) have been proposed. Such field effect transistors (hereinafter also referred to as a xe2x80x9cFETxe2x80x9d) are required to have a high withstand voltage and low loss.
A conventional FET is described by means of an example as follows. FIG. 8A shows a sectional view of a conventional FET 101 formed using Si. The FET 101 includes an n-type substrate 102, an n-type semiconductor layer 103 grown epitaxially on the substrate 102, and a p-type region 104 formed by boron implantation in the n-type semiconductor layer 103. In addition, the FET 101 also includes an n-type region 105 formed by phosphorus implantation in a part of the p-type region 104 in the vicinity of its surface, an insulating layer (a gate insulating layer) 106 formed to cover a portion of the p-type region 104 between the n-type semiconductor layer 103 adjacent to the p-type region 104 and the n-type region 105, a gate electrode 107a formed on the insulating layer 106, a source electrode 107b formed in contact with the p-type region 104 and the n-type region 105, and a drain electrode 107c formed on the rear face of the substrate 102.
In the FET 101, a bias is applied to the gate electrode 107a, so that an inversion layer is formed in the p-type region 104 and functions as a channel. In the FET 101, in order to obtain a sufficiently high withstand voltage in an off state, it is necessary to suppress a doping concentration in the n-type semiconductor layer 103 to a low level. This results in higher electrical resistance of the n-type semiconductor layer 103.
FIG. 8B shows a sectional view of a conventional FET 101a formed using SiC (silicon carbide). With reference to FIG. 8B, the FET 101a includes an n-type semiconductor layer 103 and a p-type semiconductor layer 109 grown epitaxially by a chemical vapor deposition (CVD) method sequentially-on an n-type substrate 108 made of SiC. In addition, the FET 101a also includes an n+ region 105a formed in a part of a surface portion of the p-type semiconductor layer 109. Thus, the FET 101a has an n+/p/n layered structure. The FET 101a includes a trench T passing through the p-type semiconductor layer 109 from the surface of the n+ region 105a and reaching the n-type semiconductor layer 103. The FET 101a is provided with an insulating layer (a gate insulating layer) 106 formed by oxidation of the inner wall of the trench T, a gate electrode 107a formed on the insulating layer 106, a source electrode 107b formed in contact with the n+ region 105a and the p-type semiconductor layer 109, and a drain electrode 107c formed on the rear face of the substrate 108. In the FET 101a, a channel region switched on or off depending on a voltage applied to the gate electrode 107a is formed in the vicinity of the interface between the p-type semiconductor layer 109 and the insulating layer 106 where the wall surface of the trench T is formed. The details of this conventional technique are disclosed, for example, in Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by W. J. Choyke, H. Matsunami, and G. Pensl (Akademie Verlag, 1997, Vol. II pp.369-388).
In the FET 101, the doping concentration and thickness of the n-type semiconductor layer 103 are determined depending on the withstand voltage required for the device. Generally, in order to obtain a withstand voltage of several hundreds of voltages in a Si-MOSFET, the n-type semiconductor layer 103 is required to have a thickness of several tens of micrometers and a low doping concentration of about 1014 cmxe2x88x923. Therefore, the resistance value in an on state is significantly high. Furthermore, when a thick epitaxial layer is formed at a low doping concentration in the n-type semiconductor layer 103, there have been problems in that a longer time is required for the formation and the manufacturing cost increases.
The SiC used for the FET 101a is a non-isotropic crystal. It has been known that SiC has different oxidation rates depending on crystallographic orientations. A Si plane of an xcex1-SiC(0001) substrate has the lowest oxidation rate. On the contrary, a C plane of an xcex1-SiC(000-1) substrate that is obtained by a 180xc2x0 rotation of the Si plane has the highest oxidation rate. When an insulating oxidation layer is formed by oxidation of the trench having planes corresponding to a plurality of different crystallographic orientations, the thickness of the insulating oxidation layer thus formed varies depending on the crystallographic orientations. Consequently, the thickness of the insulating silicon oxide layer is not uniform inside the trench and thus a nonuniform electric field is applied to the insulating layer 106 between the gate electrode and the SiC semiconductor. For instance, when the FET 101a is formed using the xcex1-SiC(0001) substrate with the Si plane allowing an epitaxial layer with high crystallinity to be obtained, a relatively thin insulating layer 106 is formed on the wafer surface and the bottom surface of the trench T and a relatively thick insulating layer 106 is formed on the wall surface of the trench T as shown in FIG. 8B. The gate electrode 107a also is formed on the surface of the insulating layer 106 formed on the bottom surface of the trench T. As a result, a stronger electric field than that applied to the insulating layer 106 above the channel portion positioned in the vicinity of the wall surface of the trench T is applied to the insulating layer 106 formed on the bottom surface of the trench T. In such a case, the formation of the insulating layer 106 with a sufficient thickness set with consideration given to a withstand voltage for the purpose of forming a field effect transistor with a high withstand voltage results in formation of a very thick insulating layer 106 adjacent to the channel portion (a portion of the semiconductor layer in contact with the wall surface of the trench T). The formation of the thick insulating layer 106 adjacent to the channel portion, however, causes deterioration in the response performance of the device to a gate voltage, and as a result, it is required to apply a high voltage to the gate for on/off switching of the device. When the insulating layer 106 formed adjacent to the channel portion is allowed to have an optimum thickness, there has been a problem in that the thickness of the insulating layer 106 formed on the bottom surface of the trench T is reduced and thus the withstand voltage of this portion decreases. Hence, with the above-mentioned conventional technique, it has been difficult to form a power device with a high withstand voltage and high efficiency using a substrate such as the a-SiC(0001) substrate with a Si plane.
FIG. 9 shows a power MOSFET 200 disclosed in U.S. Pat. No. 5,438,215 to Tihanyi. The FET 200 includes an n-type inner region 201, a base region 203, a source region 204, a drain region 207, a plurality of p-type additional regions 211, and n-type additional regions 212 each of which is disposed two adjacent p-type additional regions 211. The additional regions 212 are doped at a higher concentration than that at which the inner region 201 is doped.
Furthermore, in the case of the FET 200, in order to form the FET 200 with a withstand voltage of several hundreds of volts to several kilovolts using a semiconductor such as Si, it is necessary to set the length of the additional regions 211 and 212 in the thickness direction A to be several tens of micrometers or longer. In order to form such additional regions 211 and 212, it is required to repeat epitaxial growth and ion implantation plural times and thus a very complicated process is necessary. In addition, there has been a problem in that the presence of a number of interfaces formed by the repetition of the epitaxial growth results in easy breakage caused by the heat history.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a field effect transistor with a high withstand voltage and low loss, and a method of manufacturing the same.
In order to achieve the above-mentioned object, a field effect transistor of the present invention includes: an n-type semiconductor layer; a p-type semiconductor layer formed on the n-type semiconductor layer; a p-type region embedded in the n-type semiconductor layer to be in contact with the p-type semiconductor layer; a drain electrode electrically connected to the n-type semiconductor layer; an n-type source region disposed in contact with the p-type semiconductor layer; an insulating layer disposed adjacent to the p-type semiconductor layer; and a gate electrode disposed on the insulating layer. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively. According to the field effect transistor of the present invention, a field effect transistor with a high withstand voltage and low loss can be obtained.
In the field effect transistor of the present invention, the wide-gap semiconductor m ay be SiC. According to this configuration, a power device with a high withstand voltage can be obtained in which a large current can be controlled and the physical properties of SiC such as high thermal conductivity, a high withstand voltage, and the like are reflected. Particularly, a vertical field effect transistor with a high withstand voltage, large current capacity, and low loss can be obtained by using a substrate and semiconductor layers made of SiC.
In the field effect transistor of the present invention, a substrate made of SiC further may be included. The n-type semiconductor layer may be formed on the substrate. The substrate may be one of the following substrates with a Si plane: a xcex2-SiC(111) substrate, a 6H xcex1-SiC(0001) substrate, a 4H xcex1-SiC(0001) substrate, a 15R-SiC substrate, and substrates with planes obtained by off-cutting of the Si planes thereof by a tilt angle within 10 degrees. Furthermore, the substrate may be a xcex2-SiC(100) substrate, a xcex2-SiC(110) substrate, a 6H xcex2-SiC(1-100) substrate, a 4H xcex1-SiC(1-100) substrate, an xcex1-SiC(11-20) substrate, or one of those substrates with planes obtained by off-cutting of the planes thereof by a tilt angle within 15 degrees. According to the above-mentioned configuration, since a semiconductor layer with high crystallinity can be grown epitaxially, a field effect transistor can be obtained that has good characteristics and can be manufactured easily.
In the field effect transistor of the present invention, an n-type region passing through the p-type semiconductor layer to reach the n-type semiconductor layer further may be included, The n-type source region may be disposed in a surface portion of the p-type semiconductor layer and around the n-type region. A portion of the n-type source region other than its surface may be surrounded by the p-type semiconductor layer. The gate electrode may be disposed in a place corresponding to that of a portion of the p-type semiconductor layer between the n-type region and the n-type source region with the insulating layer interposed between the gate electrode and the portion of the p-type semiconductor layer. In addition, the p-type region may be disposed around the n-type region. With this configuration, a field effect transistor with a particularly high withstand voltage and low loss can be obtained.
In the field effect transistor of the present invention, a trench passing through the p-type semiconductor layer to reach the n-type semiconductor layer further may be included. The insulating layer may be disposed on at least a side wall of the trench. The n-type source region may be disposed in a surface portion of the p-type semiconductor layer and around the insulating layer. Furthermore, the p-type region may be disposed around the trench. With this configuration, a field effect transistor with a particularly high withstand voltage and low loss can be obtained.
In the field effect transistor of the present invention, the insulating layer disposed on the side wall may have a mean thickness not exceeding 500nm.
In the field effect transistor of the present invention, a total of a mean thickness of the n-type semiconductor layer and a mean thickness of the p-type semiconductor layer may not exceed 20 xcexcm. The above-mentioned configuration allows the field effect transistor to be manufactured particularly easily.
In the field effect transistor of the present invention, the p-type region may have a depth not exceeding 10 xcexcm. The above-mentioned configuration allows the field effect transistor to be manufactured particularly easily.
A method of manufacturing a field effect transistor, which is provided with an n-type semiconductor layer and a p-type semiconductor layer formed on the n-type semiconductor layer, of the present invention includes: a first process of forming the n-type semiconductor layer on an n-type substrate; a second process of forming a p-type region extending inward from a surface of the n-type semiconductor layer by doping a part of the n-type semiconductor layer; and a third process of forming the p-type semiconductor layer on the n-type semiconductor layer. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively. According to the manufacturing method of the present invention, a field effect transistor of the present invention having a high withstand voltage and low loss can be manufactured easily.
In the manufacturing method of the present invention, the following processes further may be included after the third process: a fourth process of forming an n-type region and an n-type source region by doping parts of the p-type semiconductor layer so that the n-type region passes through the p-type semiconductor layer to reach the n-type semiconductor layer, the n-type source region being disposed in a surface portion of the p-type semiconductor layer and formed around the n-type region, and a portion of the n-type source region other than its surface being surrounded by the p-type semiconductor layer; a fifth process of forming an insulating layer to cover a portion of the p-type semiconductor layer between the n-type region and the n-type source region; and a sixth process of forming a gate electrode to be disposed on the insulating layer, a source electrode to be disposed in contact with the n-type source region, and a drain electrode to be disposed on the rear face of the substrate.
In the manufacturing method of the present invention, the following processes further may be included after the third process: a fourth process of forming an n-type source region in a surface portion of the p-type semiconductor layer by doping a part of the p-type semiconductor layer; a fifth process of forming a trench to pass through the p-type semiconductor layer to reach the n-type semiconductor layer by etching a center portion of the n-type source region from a surface side of the p-type semiconductor layer so that the trench reaches the n-type semiconductor layer, and forming an insulating layer on an inner wall of the trench; and a sixth process of forming a gate electrode to be disposed inside the insulating layer, a source electrode to be disposed in contact with the n-type source region, and a drain electrode to be disposed on the rear face of the substrate.
In the manufacturing method of the present invention, the following processes further may be included after the third process: a fourth process of forming an n-type source region made of an n-type semiconductor on the p-type semiconductor layer; a fifth process of forming a trench to pass through the p-type semiconductor layer to reach the n-type semiconductor layer by etching a center portion of the n-type source region from a surface side of the n-type source region so that the trench reaches the n-type semiconductor layer, and forming an insulating layer on an inner wall of the trench; and a sixth process of forming a gate electrode to be disposed inside the insulating layer, a source electrode to be disposed in contact with the n-type source region, and a drain electrode to be disposed on the rear face of the substrate.